职位描述
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职位描述:
工作职责:
岗位职责:
1. responsible to digital module design, including specification writting, rtl code etc.
2. responsible to module verification, including test plan writing, test environment developing, test case creating and simulation.
3. assist with backend engineers on perform synthesis, timing analysis and pr of design.
任职资格:
1. good skill in verilog, systemverilog.
2. knowledge and experience with perl/tcl/makefile/shell scripts.
3. familiar with soc/mcu based on arm core.
4. familiar with amba bus protocol.
5. familiar with the peripherals (usb, ethenet, sdio, can, usart, spi, i2s, i2c, etc) of soc/mcu.
6. self-motivated and efficient to solving problems.
7. msee/ce with 3+ years of ic design experience.
工作职责:
岗位职责:
1. responsible to digital module design, including specification writting, rtl code etc.
2. responsible to module verification, including test plan writing, test environment developing, test case creating and simulation.
3. assist with backend engineers on perform synthesis, timing analysis and pr of design.
任职资格:
1. good skill in verilog, systemverilog.
2. knowledge and experience with perl/tcl/makefile/shell scripts.
3. familiar with soc/mcu based on arm core.
4. familiar with amba bus protocol.
5. familiar with the peripherals (usb, ethenet, sdio, can, usart, spi, i2s, i2c, etc) of soc/mcu.
6. self-motivated and efficient to solving problems.
7. msee/ce with 3+ years of ic design experience.
工作地点
地址:武汉洪山区上海-张江
求职提示:用人单位发布虚假招聘信息,或以任何名义向求职者收取财物(如体检费、置装费、押金、服装费、培训费、身份证、毕业证等),均涉嫌违法,请求职者务必提高警惕。
职位发布者
HR
武汉新芯集成电路制造有限公司
- 电子技术·半导体·集成电路
- 1000人以上
- 公司性质未知
- 武汉市东湖新技术开发区高新四路18号